Comprehensive Feasibility Study of Single FIN Transistors for Scaling Both Switching Energy and Device Footprint
- Resource Type
- Conference
- Authors
- Fukutome, H.; Suh, K.; Kim, W.; Moriyama, Y.; Kang, S.; Eom, B.; Kim, J.; Yoon, C.; Kwon, W.; Chung, Y.; Nam, Y.; Kim, Y.; Park, S.; Park, J.; Cho, H. -J.; Rim, K.; Kwon, S. D.
- Source
- 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2022 IEEE Symposium on. :369-370 Jun, 2022
- Subject
- Components, Circuits, Devices and Systems
Process control
Switches
Voltage
Very large scale integration
Logic gates
Transistors
Leakage currents
- Language
- ISSN
- 2158-9682
We have comprehensively studied feasibility of single-fin (1-fin) devices from viewpoint of scaling switching energy (CV 2 ) and device footprint width, which affects standard cell height. We have clarified methodology to lower minimum operation voltage (V min ) of flip-flop (F/F) featuring 1-fin devices in order to maximize gain of CV 2 . For the first time, we have demonstrated V min of 1-fin F/F same as 2-fin one and 27% CV 2 reduction with keeping speed at a constant leakage.