A hybrid design proposal for nonvolatile (NV) SRAM bit-cell is implemented in this work. Magnetic tunnel junction (MTJ) and Tunnel field effect transistor (TFET) are hierarchically integrated for ultra low leakage (ULL) and low supply voltage (V dd ) operations. Typical NV-SRAM structures are investigated with TFET replacement. Utilizing AlGaSb/InAs broken-gap heterojunctions, a novel NV-TFET-SRAM with 8T1M structure is proposed. A sub-0.5V SRAM operations and 1.65pW leakage power are realized in this hybrid bit-cell, fulfilling the needs of ultra-low dynamic power and ultra-low-leakage Internet-of-things (IoT) applications. Operation modes including normal, store, restore and reset are configured in the MTJ/TFET based 8T1M bit-cell, for writing/sensing operations in both volatile (SRAM) and non-volatile memory (MTJ). MOSFET base sensing amplifiers are evaluated with TFET implementation, for further research of more energy efficient and reliable MTJ reading.