Reconfigurable scan networks (RSNs), like IEEE Std. 1687 networks, offer flexible and scalable access to embedded (on-chip) instruments. These networks are typically accessed from the outside via a dedicated test port, like the test access port (TAP) of IEEE Std. 1149.1. As not all integrated circuits have a dedicated test port, the IEEE Std. P1687.1 working group is exploring how existing functional ports can be used. Fundamental challenges are to determine what hardware to include in the component translating information between a functional port and an IEEE Std. 1687 network and to describe a protocol for the data transported over a functional interface. We have previously shown hardware and protocol to access a limited type of IEEE Std. 1687 networks, known as flat segment insertion bit (SIB)-based networks. In this paper, we present a solution to handle general IEEE Std. 1687 networks. We have made a number of implementations with various benchmarks on an FPGA to evaluate the data overhead and the area usage.