Time Multiplexing via Circuit Folding
- Resource Type
- Conference
- Authors
- Chien, Po-Chun; Jiang, Jie-Hong R.
- Source
- 2020 57th ACM/IEEE Design Automation Conference (DAC) Design Automation Conference (DAC), 2020 57th ACM/IEEE. :1-6 Jul, 2020
- Subject
- Components, Circuits, Devices and Systems
Power, Energy and Industry Applications
Combinational circuits
Pins
Clocks
Logic gates
Field programmable gate arrays
Time division multiplexing
- Language
Time multiplexing is an important technique to overcome the bandwidth bottleneck of limited input-output pins in FPGAs. Most prior work tackles the problem from a physical design standpoint to minimize the number of cut nets or Time Division Multiplexing (TDM) ratio through circuit partitioning or routing. In this work, we formulate a new orthogonal approach at the logic level to achieve time multiplexing through structural and functional circuit folding. The new formulation provides a smooth trade-off between bandwidth and throughput. Experiments show the effectiveness of the structural method and improved optimality of the functional method on look-up-table and flip-flop usage.