VLSI Architecture of Polynomial Multiplication for BGV Fully Homomorphic Encryption
- Resource Type
- Conference
- Authors
- Hsu, Hsuan-Jui; Shieh, Ming-Der
- Source
- 2020 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2020 IEEE International Symposium on. :1-4 Oct, 2020
- Subject
- Components, Circuits, Devices and Systems
Discrete Fourier transforms
Aggregates
Hardware
Encryption
Convolution
Very large scale integration
Fully Homomorphic Encryption
Aggregate Plaintext
Cyclotomic Polynomial
Prime-factor FFT Algorithm
- Language
- ISSN
- 2158-1525
Fully homomorphic encryption (FHE) has attracted much attention because computations can be directly performed on ciphertexts. This work explores the hardware architecture of polynomial multiplication defined in BGV-FHE, targeting the applications of aggregate plaintext using cyclotomic polynomials. We show how to effectively combine the characteristics of cyclotomic polynomials and the prime-factor FFT algorithm to obtain a novel design derived by the concept of Chinese Remainder Theorem. Experimental results reveal that a significant speedup in terms of operation reduction can be achieved by adopting the proposed schemes as compared to existing works assuming a comparable security level. For example, about 2.44 and 6.34 times improvement in the total number of required modular addition and multiplication, respectively, can be obtained by using 32 one-bit aggregate slots as compared to Chen's work when the 21845-th cyclotomic polynomial is considered. The improvement could be huge if all of the available slots are involved in applications.