A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency
- Resource Type
- Conference
- Authors
- Lu, Yongjie; Sun, Yanan; He, Weifeng; Mao, Zhigang
- Source
- 2019 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) Nanoscale Architectures (NANOARCH), 2019 IEEE/ACM International Symposium on. :1-6 Jul, 2019
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Memristors
Logic gates
Layout
Resistance
Inverters
Nanoscale devices
Logic arrays
memristor crossbar
MAGIC
in-memory logic implementation
mapping
reuse
layout-friendly
area efficiency
- Language
- ISSN
- 2327-8226
The non-volatile resistive memory (memristor) is a promising device candidate for both memory and logic. The true in-memory logic computation can be realized by the stateful Memristor-Aided loGIC (MAGIC) design within memristor crossbar. The existing mapping methods targeting for the MAGIC gates however result in large crossbar array size with highly imbalanced row and column numbers. To increase the area efficiency of logic-in-memory synthesis, a new memristor-reusable mapping methodology is proposed in this paper. With the proposed mapping algorithm, the memristors storing the intermediate results are conditionally reused for multiple logic gates to guarantee a full utilization of crossbar while maintaining low operation latency overhead. A layout-friendly mapping strategy of logic gates is also developed to yield an almost-square layout. Based on the experimental results of ISCAS-85 benchmarks, the layout area of crossbar is significantly reduced by up to 95.62% on average with the proposed mapping method as compared to the previously published mapping methods. Furthermore, the proposed mapping method also reduces the product of layout area and operation latency by up to 94.03% on average as compared with the previous mapping algorithms.