A 4.8GB/s 256Mb(x16) Reduced-Pin-Count DRAM and Controller Architecture (RPCA) to Reduce Form-Factor & Cost for IOT/Wearable/TCON/Video/AI-Edge Systems
- Resource Type
- Conference
- Authors
- Shiah, C.; Chang, C.N.; Crisp, Richard; Lin, C.P.; Pan, C.N.; Chuang, C.P.; Chen, H.L.; Jheng, S.H.; Chang, T.F.; Huang, W.J.; Ting, K.C.; Dai, Rick; Huang, W.M.; Rong, B.D.; Lu, Nicky
- Source
- 2019 Symposium on VLSI Circuits VLSI Circuits, 2019 Symposium on. :C116-C117 Jun, 2019
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Power, Energy and Industry Applications
Signal Processing and Analysis
Random access memory
Pins
Arrays
Switches
Clocks
Switching circuits
Reduced-Pin-Count
DRAM
Small-Form-Factor
- Language
- ISSN
- 2158-5636
A new breed of Form-Factor-Driven DRAMs offers 80% lower standby power and > 50% IO signal reduction vs. Capacity-Driven commodity DRAM. Command/address/data are multiplexed onto 16 pins and combined with a Serial Control Pin in a Single-Edge-Pinout-Floorplan, providing bus efficiency >98%. Major SOC-DRAM subsystem cost savings are enabled via die size, packaging and PCB area savings using this RPCA. A 100x speedup of array fills using a new Group Write circuit further reduces test cost.