Compared with traditional HVDC transmission, modular multilevel converter(MMC) does not have the problems of reactive compensation and commutation failure. Besides, MMC has advantages over low harmonic components, which is more suitable to establish the multiterminal DC transmission system. As for MMC, sorting all of the capacitors’ voltages is used to achieve capacitor voltage balancing. However, if there are plenty of sub-modules (SMs) for each bridge arm, calculation amount increases a lot and sort time may lead to the failure of the capacitor voltage balancing. This paper proposes an optimization algorithm through the improvement of Quick Sort algorithm, aiming to reduce the calculation amount. By means of averaging the capacitors’ voltages with time, it is available that all of the data only needs to be divided into two parts according to the number of triggering IGBT instead of sorting all of the sub-modules. In brief, it reduces the calculation amount and switching frequency a lot theoretically. By building a bipolar MMC-HVDC model with 401level on PSCAD/EMTDC, the feasibility of this optimization algorithm can be tested and the corresponding time complexity can be analyzed as well.