Novel info wafer-level-chip-scale-package N-leak test and stress
- Resource Type
- Conference
- Authors
- Hao Chen; Hung-Chih Lin; Ching-Nen Peng; Min-Jer Wang
- Source
- 2016 e-Manufacturing and Design Collaboration Symposium (eMDC) e-Manufacturing and Design Collaboration Symposium (eMDC), 2016. :1-4 Sep, 2016
- Subject
- Components, Circuits, Devices and Systems
Engineering Profession
Fields, Waves and Electromagnetics
General Topics for Engineers
Power, Energy and Industry Applications
Signal Processing and Analysis
Metals
Stress
Resistance
Mathematical model
Semiconductor device reliability
Packaging
Parallel Test
Reliability Test
Yield Learning
InFO
WLCSP
- Language
This paper introduces a manufacturing process screening methodology for Integrated Fan Out Wafer Level Chip Scale Packaging (InFO WLCSP) which has the promise of being a very cost effective solution to achieve "More than Moore's law" for mobile devices – more so than 3D integrated circuits (3DIC). InFO WLCSP has several test challenges due to new defect modes that have never been faced before. Previous test methods take long test time and often have poor test performance. In this paper we propose test solutions that lead to a short test time and a higher test coverage for yield learning. We will demonstrate the methodology in some industrial cases to validate our claims.