Implementation of Turbo decoder using MAX-LOGMAP algorithm in VHDL
- Resource Type
- Conference
- Authors
- Mishra, Shivshankar; Shukla, Harshit; Madhekar, Suneel
- Source
- 2015 Annual IEEE India Conference (INDICON) India Conference (INDICON), 2015 Annual IEEE. :1-6 Dec, 2015
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Decoding
Bit error rate
Algorithm design and analysis
Delays
Field programmable gate arrays
Turbo codes
Error correcting codes
iterative decoding
FPGA
MAX-LOG-MAP algorithm
- Language
- ISSN
- 2325-9418
Design and implementation of a Turbo decoder on FPGA is a challenging task. Various algorithms based on the BCJR algorithm have been proposed to enable the implementation of Turbo decoding in a hardware device. With the advent of FPGAs, the realization of the BCJR algorithm and different simplified versions of BCJR algorithm on hardware is possible. A VHDL implementation of Turbo decoder using the MAX-LOG-MAP algorithm has been discussed in this paper. The target device used for this implementation is Xilinx Virtex-6 FPGA. Simulation and synthesis were carried out using ModelSim SE 6.1 and Xilinx ISE 10.1. BER plots and input and output waveforms for interleaver, deinterleaver, MAX-LOG-MAP decoder and Turbo decoder are also presented.