Quantification of interface trap density above threshold voltage by gated hall method in InGaAs buried quantum well MOSFET
- Resource Type
- Conference
- Authors
- Chidambaram, Thenappan; Madisetti, Shailesh; Greene, Andrew; Yakimov, Michael; Tokranov, Vadim; Veksler, Dmitry; Hill, Richard; Oktyabrsky, Serge
- Source
- 71st Device Research Conference Device Research Conference (DRC), 2013 71st Annual. :127-128 Jun, 2013
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
Logic gates
Capacitance
Electron traps
Charge carrier density
Electrostatic measurements
Semiconductor device measurement
Density measurement
- Language
- ISSN
- 1548-3770
Low density of states (DOS) and typically high interface and border trap densities (D it ) in high mobility group III-V semiconductors provide difficulties in quantification of D it near the conduction band edge. The trap response above the threshold voltage can be very fast, and conventional D it extraction methods, based on capacitance/conductance response (CV methods) of MOS capacitors at frequencies