Next-generation communication standards, such as OIF-CEI-25G-LR and IEEE P802.3bj, demand high-speed electrical backplane transceivers that support data rates around 25Gb/s. For such data rates and beyond, transmitter design becomes a significant technical challenge because a transmitter is the most bandwidth-hungry circuit that requires the highest clock frequency; transmitters do not use time-interleaved schemes, which are effective in reducing the clock frequency in receiver design. In conventional transceivers that use an NRZ signal having a unit-pulse-response width of 1UI, the 2-to-1 MUX for generating the 1UI pulse is the primary speed-limiting circuit and requires the highest clock frequency in the data path.