Parallel matrix algorithm autotuner on multi-core architecture
- Resource Type
- Conference
- Authors
- Zhang Ji-Lin; Ren Yong-Jian; Zhang Wei; Xu Xiang-Hua; Wan Jian; Du Jiang-Hui
- Source
- The 2nd International Conference on Information Science and Engineering Information Science and Engineering (ICISE), 2010 2nd International Conference on. :5227-5230 Dec, 2010
- Subject
- Computing and Processing
Communication, Networking and Broadcast Technologies
Sparse matrices
Conferences
Multicore processing
Optimization
Kernel
IEEE Computer Society Press
matrix multiplication
parallel
autotuner
multicore
- Language
- ISSN
- 2160-1283
2160-1291
This paper develops a performance autotuner of the parallel sparse matrix multiplication algorithm. This autotuner can utilize the cache characters of multicore computers. It can optimize the value of performance parameters in multicore and achieve the better performance of parallel matrix multiplication algorithm. This paper proposes a parallel matrix multiplication algorithm by Using the CSR compression and cache blocking technology. The cache blocking parameters are optimized to get the better performance. From the matrix experiments, we can consult that the autotuner system can achieve the sparse matrix multiplication algorithm better performance on the multicore hardware.