System level analysis and experimental characterization of frequency pulling in PLLs
- Resource Type
- Conference
- Authors
- Ranaivoniarivo, Manohiaina; Wane, Sidina; Philippe, Pascal; Aymard, Olivier; Gamand, Patrice
- Source
- SoftCOM 2010, 18th International Conference on Software, Telecommunications and Computer Networks Software, Telecommunications and Computer Networks (SoftCOM), 2010 International Conference on. :370-374 Sep, 2010
- Subject
- Communication, Networking and Broadcast Technologies
Computing and Processing
Phase locked loops
SAW filters
Voltage-controlled oscillators
Charge pumps
Power amplifiers
Power generation
Transfer functions
- Language
In this paper a system-level experimental characterization and analysis of pulling in phase-locked-loops (PLL) is presented. Competitive effects originating from integrated IC (chip-level) through the PLL loop and the power amplifier (PA) are investigated taking into account coupling with SAW filter on PCB-level. Physical interpretation of observed pulling effects which result from combined influences of PLL loop, PA block and SAW filter module are proposed to sustain a global behavioral modeling using Matlab Simulink facilities, and Cadence Verilog-AMS tooling.