A 65nm CMOS 3.6GHz fractional-N PLL with 5th-order ΔΣ modulation and weighted FIR filtering
- Resource Type
- Conference
- Authors
- Yu, Xueyi; Sun, Yuanfeng; Rhee, Woogeun; Ko, Sangsoo; Choo, Wooseung; Park, Byeong-Ha; Wang, Zhihua
- Source
- 2009 IEEE Asian Solid-State Circuits Conference Solid-State Circuits Conference, 2009. A-SSCC 2009. IEEE Asian. :77-80 Nov, 2009
- Subject
- Components, Circuits, Devices and Systems
Signal Processing and Analysis
Engineered Materials, Dielectrics and Plasmas
Phase locked loops
Finite impulse response filter
Phase noise
Bandwidth
Digital modulation
Digital filters
Filtering
Noise reduction
Prototypes
1f noise
- Language
A 3.6GHz fractional-N PLL utilizing high-order digital modulation and weighted 13-tap finite impulse response (FIR) filtering for low spur and enhanced noise reduction is implemented in 65nm CMOS. The prototype PLL exhibits nearly −100dBc/Hz in-band noise contribution and −126.8dBc/Hz phase noise at a 3MHz offset from a 1.8GHz carrier. With 5 th -order single-loop ΔΣ modulation, the fractional spur levels of −65.6dBc and −58.5dBc are achieved within the bandwidth and near the bandwidth, respectively.