Quality considerations in delay fault testing
- Resource Type
- Conference
- Authors
- Pierzynska, A.; Pilarski, S.
- Source
- Proceedings of EURO-DAC. European Design Automation Conference Design automation Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European. :196-201 1995
- Subject
- Computing and Processing
Communication, Networking and Broadcast Technologies
Circuit testing
Circuit faults
Delay estimation
Propagation delay
Electrical fault detection
Fault detection
Logic testing
Logic circuits
Semiconductor device modeling
Very large scale integration
- Language
We examine delay model used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which significantly affect the actual delays, but which are not taken into account by the existing model used in testing. Our analysis questions the test quality offered by test generation procedures used so far.