A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC
- Resource Type
- Conference
- Authors
- Kim, Young-Ju; Choi, Hee-Cheol; Yoo, Pil-Seon; Lee, Dong-Suk; Choi, Joong-Ho; Lee, Seung-Hoon
- Source
- APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on. :17-20 Nov, 2008
- Subject
- Components, Circuits, Devices and Systems
Communication, Networking and Broadcast Technologies
Engineered Materials, Dielectrics and Plasmas
Voltage
Sampling methods
Circuits
Operational amplifiers
Capacitors
Rail to rail inputs
Energy consumption
Clocks
Railway engineering
Power engineering and energy
- Language
A 12b 2MS/s cyclic ADC achieves low power consumption with a single-ended rail-to-rail input signal range of 3.3Vp-p. The proposed voltage reference scheme directly employing power supply voltages implements an offset voltage less than 1mV without well-known calibration and trimming techniques. The prototype ADC in a 0.18μm CMOS technology demonstrates the effective number of bits of 11.48 for a 100kHz full-scale input at 2MS/s. The ADC with an active die area of 0.12mm 2 consumes 3.6mW at 2MS/s and 3.3V(analog)/1.8V (digital).