Performance Improvement and Low Power Design of Embedded Processor
- Resource Type
- Conference
- Authors
- Jung, Hongkyun; Kim, Hyoungjun; Kang, Kwangmyoung; Ryoo, Kwangki
- Source
- 2008 Third International Conference on Convergence and Hybrid Information Technology Convergence and Hybrid Information Technology, 2008. ICCIT '08. Third International Conference on. 2:140-145 Nov, 2008
- Subject
- Computing and Processing
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Process design
Clocks
Prediction algorithms
Pipelines
Cache memory
Memory management
Reduced instruction set computing
Field programmable gate arrays
Frequency
Timing
OpenRISC
branch prediction
cache
clock-gating
ODC
- Language
This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of 32-bit RISC processor and a clock gating algorithm using ODC (Observability Don't Care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache using pseudo LRU(Least Recently Used) algorithm. The proposed algorithm is applied to OpenRISC1200 processor, embedded processor and implemented on Xilinx VIRTEX-4 XC4VLX80 FPGA device and the FPGA executes at the maximum frequency of 53.042MHz. As a result of estimation of performance and dynamic power, the performance of the OpenRISC1200 processor using the proposed algorithm is improved about 5~9% and dynamic power of the processor using Samsung 0.18µm technology library is reduced by 13.9%.