An Efficient Design-for-Testability Scheme for Motion Estimation in H.264/AVC
- Resource Type
- Conference
- Authors
- Wu, Tung-Hsing; Tsai, Yi-Lin; Chang, Soon-Jyh
- Source
- 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on. :1-4 Apr, 2007
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Signal Processing and Analysis
Motion estimation
Automatic voltage control
Circuit testing
Adders
Logic testing
Logic arrays
Circuit faults
Circuit synthesis
Circuit simulation
Timing
- Language
In this paper, a complete analysis for the input combinations of balanced and unbalanced adder trees based on C-testability conditions is presented. Based on the analysis, a simple and efficient design-for-testability scheme is proposed to implement the testable design for Motion Estimation (ME) circuit in H.264/AVC. The proposed testable scheme is applied to bit-level regular arrangement for the variable-block-size ME architecture. It guarantees 100% fault coverage with only 8 sets of test patterns. The proposed circuit design was synthesized with TSMC 0.13 μm technology. Simulation results show that the proposed design only increases about 6.5% area overhead compared to the original ME circuit with acceptable timing penalty.