Built-in self-test design for large embedded PLAs
- Resource Type
- Conference
- Authors
- Pierzynska, A.; Pilarski, S.
- Source
- Digest of Papers. 1992 IEEE VLSI Test Symposium VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE. :73-78 1992
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Signal Processing and Analysis
Built-in self-test
Programmable logic arrays
Circuit testing
Process design
Combinational circuits
Test pattern generators
Automatic testing
Compaction
Performance evaluation
Circuit faults
- Language
Proposes a new easily testable PLA. In the design process the authors use a simple property of relatively prime numbers. The PLA can be efficiently integrated with random pattern techniques used for testing combinational circuits. In the proposed implementation, test pattern generation and test response compaction are performed by circular self-test path (circular BIST). Very high fault coverage can be achieved in a feasible testing time.ETX