Among existing analog-to-digital converter (ADC) architectures, the Flash ADC is a well-known topology that is primarily characterized by its processing speed and is widely used in systems that require fast information response. Research is increasingly focused on reducing the power consumption and extending the operating range of these ADCs. In this paper, we present the design of a 4-bit 20 MS/s low-power Flash ADC in a 65-nm CMOS. In addition, the design of comparators that can provide rail-to-rail inputs was proposed, enabling an extended operating range for the ADC. Finally, we achieved a total power consumption of 104 $\mu \mathrm{W}$, with a signal-to-noise ratio (SNR) and spurious-sensitive dynamic range (SFDR) of 25.09 dB and 36.46 dB, respectively, an effective number of bits (ENOB) of 3.87 bits, and a figure of merit (FoM) of 355 fJ/conv-step.