CRYSTALS-Kyber is a powerful Post-Quantum Cryptography(PQC) with high resistance to quantum computer attacks. In order to optimize the core sampling structure of Kyber so as to improve the hardware execution efficiency, this paper proposes a high-performance rejection sampling hardware circuit design scheme for Kyber. The scheme first divides the input random numbers by width converter, and then combines four parallel sampling cores to shorten the sampling time period; then on the basis of the high parallelization of sampling cores, this work use the reorganization of random numbers and the bit-weighted value characteristics of binary numbers to design high-efficiency comparator to reduce the rejection rate, and reduce the sampling time and overhead; and finally, splice the valid inputs and set up a buffer to store the generated samples. The scheme is verified for its performance by testing under Taiwan Semiconductor Manufacturing Company(TSMC) 65nm process and FPGA implementation under Vivado platform. The experimental results demonstrate that the optimized sampling circuit reduces the rejection rate from 18.73% to 11.33% and shortens the sampling clock period by 80.84% compared to the basic implementation; comparing with the related work, it reduces the area by 67.77% while controlling the sampling time, and the consumption of hardware resources is greatly reduced, which improves the efficiency of the hardware execution of the Kyber rejection sampling.