General Vector Instruction Extension for GF(2m) Polynomial Operation in Post-quantum Cryptography
- Resource Type
- Conference
- Authors
- Kuang, Honglin; Zhao, Yifan; Sun, Yi; Han, Jun
- Source
- 2023 IEEE 15th International Conference on ASIC (ASICON) ASIC (ASICON), 2023 IEEE 15th International Conference on. :1-4 Oct, 2023
- Subject
- Components, Circuits, Devices and Systems
Neon
Costs
Bandwidth
Hardware
Cryptography
Kernel
Post-quantum cryptography
BIKE
Polynomial multiplication
Polynomial inversion
Vector ISA extension
- Language
- ISSN
- 2162-755X
We present a general vector instruction extension applicable for both ARM NEON and RISC-V Vector Extension. The extension targets efficient bit-manipulation and can provide considerable speedup for applications in GF(2 m ) such as code-based post-quantum cryptography schemes. The effectiveness of the extension is evaluated by using the custom instructions to optimize the kernel operations in BIKE key-encapsulation schemes. We first innovate vectorized versions of bit-polynomial multiplication and inversion algorithms in GF(2 m ) and propose vector instruction extension. Furthermore, a configurable hardware unit has been proposed to support custom operations of different bandwidths at little cost and constant latency. Both experiments on Xilinx UltraScale+ ZCU104 for ARM and simulations on gem5 for RISC-V have been carried out. Compared to portable C implementation, the result shows a speedup for bit-polynomial multiplication and inversion of up to 13x and 16x in ARM, 13x and 22x in RISC-V respectively.