High-performance computing (HPC) and big data computing (BDC) play the most important role because it can perform calculations quickly and accurately, requiring billions or trillions of transistors to support the results. These HPC and BDC designs larger chip sizes and package sizes, resulting in very low yield and experience costs. What the electronics industry is doing is breaking down large chips into small chip-based devices to increase yields and reduce overall costs. Chiplet packaging has become a key technology for continuation of Moore's Law. Many package types were developed for this purpose including 2.5D, 3D, EMIB and Fan-out family. (FO-MCM, FO-EB and FO-EB-T). In this article, we will introduce FO- EB- T packaging technology (Fan-Out Embedded Bridge TSV). Based on package structure of view, the difference between FO- EB and FO- EB- T package is on embedded die structure. The benefit of FO- EB- T come from better electric performance (compared to FO-EB package) and lower package cost (compared to 2.5D package) better warpage control (compared to FO- MCM package). The paper will also demonstrate FO- EB- T package design (interconnection for SOC with HBM), simulation and measurement of electrical performance (reduce AC noise and power enhancement) and warpage mismatch.