Driving by AI and 5G, advanced packaging technology focuses more on homogeneous integration and heterogeneous integration of chiplets to meet the requirement of high computing performance, low latency, and high-density interconnection. Fan out wafer level package (FOWLP) efficiently enables higher I/O counts for high performance edge computing by re-distribution organic layers (RDL). Therefore, in this study we propose a fan out multi-chip module (FO-MCM) with chip-first process for the homogeneous integration. Compared with FO-MCM chip last solution, due to the short assembly process step, it can save FO materials and FO processing costs and provide customers with lower cost options and better high frequency signal integrity for their product design requirement. In this paper, we adopt FO-MCM with chip first process to have a test vehicle (TV) case study. The construction of top die is fabricated thru bumping process and build up multiple RDL layers by plating process and copper bumping pad in face-up orientation. In comparison of Fan-out technology with chip last process, the structure without under-fill material as a buffer layer has the stress concern in this TV case development. Regarding the RDL and via simulation for mechanical optimization, there are three factors which can provide a structure selection to reduce stress on passivation layers and RDL layers. The study is to focus on passivation layer thickness, C4 bumping structure, and C4 UBM size. The result indicates the thicker passivation thickness, more solder volume in bump structure and narrow UBM size can reduce RDL and passivation peeling stress to avoid RDL and passivation defect risk during reliability test. The test vehicle has been passed reliability verification by TCG 1000x, u-HAST 96hrs and HTST 1000hrs.