Fast and compact dynamic ripple carry adder design
- Resource Type
- Conference
- Authors
- Chih-Jen Fang; Chung-Hsun Huang; Jinn-Shyan Wang; Ching-Wei Yeh
- Source
- Proceedings. IEEE Asia-Pacific Conference on ASIC, Asia-Pacific conference on ASIC ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on. :25-28 2002
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Adders
CMOS logic circuits
Logic design
Propagation delay
Switches
SPICE
Circuit simulation
Very large scale integration
Arithmetic
Voltage
- Language
Adders are fundamental building blocks and often constitute part of the critical path. In this paper, we propose four high-speed ripple carry adder designs using dynamic circuit techniques. CMOS technology based SPICE simulations show that the proposed dynamic ripple carry adders are at least two times faster than the conventional static ripple carry adder. Further, all of the proposed designs compare much favorably to a previous dynamic ripple carry adder design that employs DCVS (differential cascode voltage switch) logic.