A 40 kS/sCalibration-Free Incremental △Σ ADC Achieving 104 dB DR and 105.7 dB SFDR
- Resource Type
- Conference
- Authors
- Mokhtar, Mohamed A.; Ismail, Omar; Vogelmann, Patrick; Kauffman, John G.; Ortmanns, Maurits
- Source
- ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC) Solid State Circuits Conference (ESSCIRC), ESSCIRC 2023- IEEE 49th European. :401-404 Sep, 2023
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Photonics and Electrooptics
Signal Processing and Analysis
Quantization (signal)
Linearity
Europe
Bandwidth
Delta-sigma modulation
Sensors
Calibration
- Language
- ISSN
- 2643-1319
High dynamic range (DR) Nyquist-rate ADCs are needed in many sensing applications. While noise-and mismatch-error shaping realize power efficient designs, they prevent true Nyquist-rate operation. We propose to combine variable-bitwidth operation and recuperation phase in an incremental Delta-Sigma modulator which allow to achieve intrinsic linearity combined with reduced quantization noise. The design achieves 105. 7dB SFDR and 104 dB DR over a 20 kHz bandwidth with $\mathrm{F}\mathrm{o}\mathrm{M}_{\mathrm{D}\mathrm{R}}$=180dB without calibration or randomization.