High Efficiency Variation-Aware SRAM Timing Characterization via Machine-Learning-Assisted Netlist Extraction
- Resource Type
- Periodical
- Authors
- Jeon, I.; Park, H.; Yoon, T.; Jeong, H.
- Source
- IEEE Transactions on Circuits and Systems II: Express Briefs IEEE Trans. Circuits Syst. II Circuits and Systems II: Express Briefs, IEEE Transactions on. 71(3):1391-1395 Mar, 2024
- Subject
- Components, Circuits, Devices and Systems
Manganese
Random access memory
Transistors
Optimization
Integrated circuit modeling
Voltage
SPICE
Bayesian optimization
netlist reduction
postlayout simulation
static-random access memory
timing characterization
- Language
- ISSN
- 1549-7747
1558-3791
This brief presents a highly efficient methodology for reducing SPICE netlist and characterizing variation-aware timing, utilizing machine learning to reduce simulation time. We present a netlist reduction algorithm that automatically extracts critical path components using several exclusion rules. We then employ simplified RC model on the extracted critical path, where the parasitic RC values are determined through Bayesian Optimization. Our method reduces the number of transistors by 95.2-98.7% compared to the original and speeds up the simulation time by 26-105x compared to the conventional 1000 sample Monte Carlo with the post-layout, with an accuracy loss of below 3.63%.