A 12nm 137 TOPS/W Digital Compute-In-Memory using Foundry 8T SRAM Bitcell supporting 16 Kernel Weight Sets for AI Edge Applications
- Resource Type
- Conference
- Authors
- Jedhe, Gajanan; Deshpande, Chetan; Kumar, Sushil; Xue, Cheng-Xin; Guo, Zijie; Garg, Ritesh; Jway, Kim Soon; Chang, En-Jui; Liang, Jenwei; Wan, Zhe; Pan, Zhenhao
- Source
- 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2023 IEEE Symposium on. :1-2 Jun, 2023
- Subject
- Components, Circuits, Devices and Systems
Random access memory
Computer architecture
Very large scale integration
FinFETs
Foundries
Silicon
Kernel
- Language
- ISSN
- 2158-9682
This paper presents a Digital Compute-In-Memory design in 12nm FinFET technology with capacity to store weights for 16 kernels per input channel. This macro is designed using an 8T SRAM push-rule foundry bitcell with integrated kernel selection and multiplication for an AI Edge application that achieves 30% better TOPS/mm 2 without loss of TOPS/W than a comparable logic-rule custom bitcell based architecture on the same silicon. We present novel power saving architectures, Activation Based Precharge and Folded Kernel Selector that achieves 11.2 TOPS/mm 2 and 137 TOPS/W with highest reported 16 kernels per input channel. Further, we showcase novel design circuitry to reduce peak current by 69.1% using a new Precharge During Write scheme.