Benchmark DPC++ code and performance portability on heterogeneous architectures
- Resource Type
- Conference
- Authors
- Mijic, Nenad; Davidovic, Davor
- Source
- 2023 46th MIPRO ICT and Electronics Convention (MIPRO) ICT and Electronics Convention (MIPRO), 2023 46th MIPRO. :331-337 May, 2023
- Subject
- Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Photonics and Electrooptics
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Performance evaluation
Codes
Source coding
Graphics processing units
C++ languages
Benchmark testing
Programming
code portability
DPC++
GPU
MPI
HPC
Choleksy QR2
- Language
- ISSN
- 2623-8764
Source code portability is becoming increasingly important in the development of new solutions in HPC due to the wide diversification of hardware and heterogeneity of systems. With Intel’s oneAPI suite of programming tools and the Data Parallel C++ compiler, a single source code containing both host and device code can leverage hardware architectures from different vendors. Using the compiler’s interoperability, it can be linked to existing libraries such as MPI to run the program on a distributed memory system. In this paper we benchmark and analyze the performance that can be achieved with the Intel DPC++ compiler, using the distributed Cholesky QR2 algorithm as an example and comparing it with the native CUDA and C++ implementation. The analysis shows that the performance degradation when using SYCL is negligible when a smaller number of nodes are used, but with the cost that some additional self-made optimizations are required in SYCL code.