A power amplifier (PA) structure based on outphasing operation, dynamic power control and voltage-current combiner is proposed for high efficiency operation at power back-off (PBO). The overall PA circuits are divided into eight units to realize three power modes for dynamic power control. Serial connected inductors and capacitors are used to implement a voltage-current combiner. Parallel inductors are used to resonate the parasitic capacitance at output nodes. Based on 65nm CMOS process, the total layout size of the PA is 1.4*1.6 mm 2 . The post-layout simulation results show the peak power of 23.8 dBm, the peak drain efficiency of 33% at 2.4 GHz, and 18.8% with 6 dB power back-off. The proposed PA achieves drain efficiency of 1.26 times, 1.15times and 1.3 times of theoretical class B PA at 3dB, 6dB, 9dB power back-off respectively.