A 128 Gbit/s 3D-Integrated Silicon Photonics Receiver with 1.5 pJ/bit Power Consumption
- Resource Type
- Conference
- Authors
- Wu, Dingyi; Wang, Dong; Chen, Daigao; Yan, Jie; Dang, Ziyue; Feng, Jianchao; Chen, Shiping; Feng, Peng; Zhang, Hongguang; Fu, Yanfeng; Wang, Lei; Hu, Xiao; Xiao, Xi
- Source
- 2022 Asia Communications and Photonics Conference (ACP) Asia Communications and Photonics Conference (ACP), 2022. :1509-1513 Nov, 2022
- Subject
- Communication, Networking and Broadcast Technologies
Photonics and Electrooptics
Power demand
Three-dimensional displays
Receivers
Bandwidth
Silicon photonics
Photodetectors
Flip-chip devices
3D Integration
Ge-Si Photodetector
TIA
Flip-chip technology
- Language
A 100 Gbit/s NRZ and 128 Gbit/s PAM-4 3D-integrated silicon photonics receiver with low power consumption is reported. The receiver is implemented based on flip-chip 3D integration with a germanium-silicon (Ge-Si) photodetector (PD) and a commercial linear transimpedance amplifiers (TIA).