The large scale floating point matrix operations are widely used in numerical analysis, image processing and signal processing. This paper studies the design and implementation of the complex floating-point matrix multiplication operations based on high level synthesis (HLS), mainly including the design and implementation of complex floating-point matrix operation architecture, the large-scale RAM model, and the random matrix verification platform. The complex-floating-point multiplication and accumulation array is designed by HLS approach, the large-scale complex floating point matrix-vector multiply operation is implemented by instancing and paralleling the arrays, and the chip development period is greatly shorted. The correctness of complex matrix operation is verified by establishing a random verification platform. The operation latency is only 22 cycles for the 32-dimension complex-floating-point matrix multiplication at a clock cycle of 800MHz, that is only 27.5ns to implement the matrix-vector multiplication operation under the pipelining processing and the circuit meets the timing requirements.