Next generation receivers, such as the direct $\Delta \Sigma $ receiver (DDSR), shift the boundary between analog and digital closer to the antenna by merging the functionalities of different sub-blocks. In the DDSR, the analog components are used to their maximum potential as each stage participates in amplification, blocker filtering, anti-aliasing, and quantization noise shaping simultaneously, resulting in a compact design. To overcome the increased design complexity, the implemented DDSRs rely on common practices in receiver and $\Delta \Sigma $ modulator design. In this paper, we will show that the common design practices for neither receivers nor $\Delta \Sigma $ modulators yield optimal performance for the DDSR, and propose a systematic design method for $\textit{g}_{\text {m}}$ C based DDSRs. The method enables improved performance and a straight-forward design flow by combining the gain partitioning, noise considerations, and loop-filter design. The developed method is demonstrated by designing a gmC based DDSR using a 28nm FDSOI CMOS process. Simulations of the DDSR indicate state-of-the-art performance. [ABSTRACT FROM AUTHOR]