The Impact of Gate Leakage Current on PLL in 65 ㎚ Technology
Analysis and Optimization
- Resource Type
- Academic Journal
- Authors
- Jing Li; Ning Ning; Ling Du; Qi Yu; Yang Liu
- Source
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE. 2012-03 12(1):99-106
- Subject
- Phase-locked loop
jitter
ring voltagecontrolled oscillator
voltage-to-voltage circuit
gate leakage current
- Language
- Korean
- ISSN
- 1598-1657
2233-4866
For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phaselocked loop (PLL) is analyzed and modeled. A voltage-to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on Vctrl induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 ㎚ CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 ㎒ output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively