There is provided a matrix operation device comprising a k201-th power weighting multiplication circuit (202) for weighting inputs with k201-th power weighting coefficients (202b) which are obtained by multiplying weighting coefficients (202a) by 2 to the k201-th power and then integerizing the product, a k202 bit shift multiplication circuit (206) for performing bit-shift multiplication by k202 bit shift on the multiplication result of the k201-th power weighting multiplication circuit (202), a correction circuit (207) for adding a correction value to the multiplication result of the k202 bit shift multiplication circuit (206), a round-off circuit (204) for rounding off the operation result of the correction circuit (207), and an n bit shift division circuit (205) for performing bit shift division by n bit shift (n=k201+k202) on the operation result of the round-off circuit (204). Thereby, the amount of operation is reduced to reduce the circuit scale, and operation accuracy is improved.