In this paper, low noise CMOS image sensor(CIS) with dual correlated double sampling (CDS) technique is presented. To design low noise CIS, the proposed CDS is designed with Up/down counter which has memory and subtraction function. A two-step single slope ADC(TS-SS ADC) is used for high-speed operation and 4-input comparator is used to implement a TS-SS ADC instead of using a 2-input comparator. Many errors about switching and parasitic noise can be reduced by using 4-input comparator. A two-step single slope ADC in each column is proposed to obtain 12-bit resolution. With these techniques, the A/D converter operates more speed compared with the single-slope ADC type, and the ADC area in each column less than the previous two-step single slope ADC. The proposed CIS has been fabricated with 90nm 1-poly 5-metal backside illumination (BSI) CIS process and Array format is a Full HD (1920 x 1440)