With the development of semiconductor technology and radio frequency circuit design level, RF CMOS technology has made great improvement on price, power consumption and reliability. It is available to design good performance SOC with CMOS technology, such as RFID system.In this thesis, a fractional-n phase-locked loop frequency synthesizer implemented with 0.13 um process is presented. In a RFID reader system, a frequency synthesizer is used to supply local signal. The performance of frequency synthesizer performance has an important effect on the reader system. The frequency synthesizer presented in this thesis consist of a phase / frequency detector (PFD), a charge pump (CP), a 3rd passive loop filter (LPF), a LC-voltage control oscillation (LC-VCO), a pulse swallow divider (P.S. divider) and a 3rd MASH 1-1-1 delta sigma modulator (DSM). The PFD dead-zone problem is mitigated with proper time delay on reset time. And TSPC DFF is used in PFD design. It can work in high speed and occupies small area. The CP is implemented with a structure with two compensators to reduce the current mismatch and variation. During VCO working ranges, the current mismatch is less than 3.4 %. The LC-VCO with a manual high Q inductor exhibits a good noise performance. P.S. divider is designed with 8 control bits. Its maximum dividing ratio is 257. The 3rd delta sigma modulator implemented with a scheme of MASH 1-1-1.The frequency synthesizer area is 1755 um*1644 um. Integer-n PLL noise is -117.16dBc@200KHz. The fractional-n PLL noise performance is not good. It is less than -90dBc@200KHz.