A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS
- Resource Type
- Conference
- Authors
- Wu, Wanghua; Bai, Xuefei; Staszewski, Robert Bogdan; Long, John R.
- Source
- 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International. :352-353 Feb, 2013
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Phase locked loops
Metals
Solid state circuits
CMOS integrated circuits
Strips
Frequency shift keying
- Language
- ISSN
- 0193-6530
2376-8606
Frequency synthesis at mm-Waves is still dominated by analog PLLs, although all-digital PLLs (ADPLLs) [1] have been widely explored below 10GHz. The major obstacle has been the poor quality of digitally controlled oscillators (DCO) as MOS varactor Q-factor drops to