Twin-Tub CMOS II-An advanced VLSI technology
- Resource Type
- Conference
- Authors
- Parrillo, L.C.; Wang, L.K.; Swenumson, R.D.; Field, R.L.; Melin, R.C.; Levy, R.A.
- Source
- 1982 International Electron Devices Meeting IEDM Tech. Dig. Electron Devices Meeting, 1982 International. :706-709 1982
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
Very large scale integration
CMOS technology
Circuits
Threshold voltage
Implants
Protection
Isolation technology
Oxidation
Electric resistance
Etching
- Language
An advanced CMOS technology has been developed for the fabrication of VLSI circuits having 2.5 µm features. The structure uses Twin-Tubs in a lightly-doped n-epitaxial layer over an n + -substrate 2 . Local oxidation and self-aligned chan-stops provide device isolation. The gate level has a nominal sheet resistance of 2.5Ω/□ and consists of a composite layer of TaSi 2 over n + polysilicon. The gate oxide is 350 Å thick, and the electrical channel lengths for the n- and p-channel transistors are nominally 1.5 µm The threshold voltages of the n- and p-channel devices are 0.7V and -1.1V respectively. A compensating threshold-adjustment implant is used to tailor the p-channel threshold voltage. The limitations and advantages of this technique are addressed here. We present the process highlights discuss the device properties and present some of the applications of this technology.