A 28-GHz Series-Parallel Combined Doherty Power Amplifier with PBO Efficiency Enhancement in 40nm Bulk CMOS
- Resource Type
- Conference
- Authors
- Gu, Junjie; Qin, Haoqi; Jin, Guixiang; Xu, Hao; Liu, Weitian; Han, Tingting; Tian, Mi; Zhu, Weiqiang; Yan, Na
- Source
- 2022 IEEE MTT-S International Wireless Symposium (IWS) Wireless Symposium (IWS), 2022 IEEE MTT-S International. 1:1-3 Aug, 2022
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Signal Processing and Analysis
Wireless communication
6G mobile communication
5G mobile communication
Power amplifiers
Bandwidth
CMOS process
Power generation
Doherty Power Amplifier
PBO Efficiency Enhancement
Transformer-based Passive Network
5G mm-Wave
- Language
In this paper, a series-parallel combined Doherty power amplifier is proposed. The Doherty architecture is adopted for PBO efficiency enhancement. The power-combining structure is applied for the improvement of saturated output power. The PA is designed in a 40nm bulk CMOS process to achieve a saturated output power of 23dBm and a peak power-added efficiency of 40%. The 6-dB back-off power-added efficiency achieves 26%, indicating obvious efficiency improvement owing to Doherty architecture. The 3-dB bandwidth of the proposed power amplifier is over 6GHz, and OP1dB exceeds 20 dBm in 25–31 GHz.