Reliable techniques of leakage current reduction for SRAM-6T Cell: A review
- Resource Type
- Conference
- Authors
- Chauhan, Ankita; Chauhan, D. S.; Sharan, Neha
- Source
- 2016 3rd International Conference on Computing for Sustainable Global Development (INDIACom) Computing for Sustainable Global Development (INDIACom), 2016 3rd International Conference on. :2251-2254 Mar, 2016
- Subject
- Bioengineering
Communication, Networking and Broadcast Technologies
Computing and Processing
Engineering Profession
General Topics for Engineers
Geoscience
Nuclear Engineering
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Transportation
Transistors
Logic gates
Leakage currents
Tunneling
MOS devices
Random access memory
Junctions
Gated Vdd
Leakage component
MTCMOS SRAM
Transistor stacking
Source biasing
- Language
Feature size of the transistor is shrinking by the rapid progress in semiconductor technology in deep sub-micron (DSM) technology. At the present time; these days's leakage power is more important in hardware's and microprocessors. Memory contains large number of transistor in advanced computer system. Mainly the leakage dissipation is directly related to the no. of transistors. As technology scaling static random memory in standby leakage power is becoming one of the more important concerns for low power application. In this paper we have study of different leakage components of sram cell and some leakage reduction techniques like Gated Vdd, MTCMOS, transistor stacking, source biasing and negative word line scheme approach to optimizing low leakage in sram memory cell.