A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology
- Resource Type
- Conference
- Authors
- Chen, Wei-Zen; Lu, Tai-You; Wang, Yan-Ting; Jian, Jhong-Ting; Yang, Yi-Hung; Huang, Guo-Wei; Liu, Wen-De; Hsiao, Chih-Hua; Lin, Shu-Yu; Liao, Jung Yen
- Source
- 2012 Symposium on VLSI Circuits (VLSIC) VLSI Circuits (VLSIC), 2012 Symposium on. :12-13 Jun, 2012
- Subject
- Components, Circuits, Devices and Systems
Communication, Networking and Broadcast Technologies
Computing and Processing
Harmonic analysis
Mixers
Phase locked loops
Voltage-controlled oscillators
Power harmonic filters
CMOS integrated circuits
PLL
THz
Mixer
RSSI
- Language
- ISSN
- 2158-5601
2158-5636
A 160-GHz receiver-based PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3 rd harmonic mixer incorporating frequency tripler for frequency down conversion. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatically frequency sweeping and fast locking. The frequency locking time is less than 3 µsec. Fabricated in 65 nm CMOS technology, the chip size is 0.92mm 2 . This chip drains 24mW from a 1.2V power supply.