Power-aware automatic constraint generation for FPGA based real-time video processing systems
- Resource Type
- Conference
- Authors
- Lawal, Najeem; Thornberg, Benny; O'Nils, Mattias
- Source
- Norchip 2007 Norchip, 2007. :1-5 Nov, 2007
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Power generation
Field programmable gate arrays
Real time systems
Power system modeling
Digital signal processing
Neck
Routing
Automatic programming
Energy consumption
Resource management
- Language
The introduction of embedded DSP blocks and embedded memory has made FPGAs an attractive architecture for implementation of real-time video processing systems. The big bottle neck of the FPGA compared to other programmable architectures is the complex programming model. This paper presents an automatic generation of placement and routing constraints for FPGA implementation of real-time video processing systems as one step to automate the programming model. The constraint generator targets lower power consumption, better resource utilization and reduced development time. Results show that a 28 % reduction in dynamic power can be achieved using the proposed approach over traditional logic to memory mapping.