Use of test structures for a wafer-level-reliability monitoring
- Resource Type
- Conference
- Authors
- Papp, A.; Bieringer, F.; Koch, D.; Kammer, H.; Pohle, H.; Schlemm, A.; Schneegans, M.; Vogt, H.
- Source
- Proceedings of International Conference on Microelectronic Test Structures Microelectronic test structures Microelectronic Test Structures, 1996. ICMTS 1996. Proceedings. 1996 IEEE International Conference on. :267-271 1996
- Subject
- Components, Circuits, Devices and Systems
Monitoring
Stress
Production
Circuit testing
Feedback
Life testing
Automatic testing
Semiconductor device reliability
Life estimation
Electromigration
- Language
To fulfil future quality requirements, the waferfabs need a fast feedback of reliability data additionally to that already established for yield data. Wafer-level-reliability programs for test structures with highly accelerated stress are necessary to reach very short test periods. A concept with a variable drop-in test chip is described. By means of two examples, gate oxide integrity and electromigration, challenges and solutions are presented. The charge to breakdown distribution offers a way to characterize early failures rapidly. The EM test on wafer level allows life time predictions to remain useful.