Behavioral Implementation of SVD on FPGA
- Resource Type
- Conference
- Authors
- TIAN, Mi; SIMA, Mihai; McGUIRE, Michael
- Source
- 2018 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT) Signal Processing and Information Technology (ISSPIT), 2018 IEEE International Symposium on. :495-500 Dec, 2018
- Subject
- Bioengineering
Computing and Processing
Robotics and Control Systems
Signal Processing and Analysis
Field programmable gate arrays
Jacobian matrices
Mathematical model
Hardware
Matrix decomposition
Computer architecture
Routing
- Language
Implementing Singular-Value Decomposition (SVD) in real time is a requirement in wireless communications. Pure-software solutions are not likely to provide a satisfactory computing speed; thus, hardware support is needed. Field-Programmable Gate Arrays (FPGA) can provide a cost-effective alternative to full-custom hardware as long as the digital design is tuned toward the specific reconfigurable architecture. In this paper, we describe techniques to generate a behavioral implementation of SVD that can be mapped easily onto FPGA, thereby reducing the effort of the design and coding. The computing performance and hardware complexity are in line or better than prior-art.