Automating the design of SOCs using cores
- Resource Type
- Periodical
- Authors
- Bergamaschi, R.A.; Bhattacharya, S.; Wagner, R.; Fellenz, C.; Muhlada, M.; White, F.; Daveau, J.-M.; Lee, W.R.
- Source
- IEEE Design & Test of Computers IEEE Des. Test. Comput. Design & Test of Computers, IEEE. 18(5):32-45 Jan, 2001
- Subject
- Computing and Processing
Logic
System-on-a-chip
Protocols
LAN interconnection
Pins
Manufacturing
Libraries
Assembly systems
Microelectronics
System testing
- Language
- ISSN
- 0740-7475
1558-1918
Assembling a system on a chip using IP blocks is an error-prone, labor-intensive, and time-consuming process. Emerging high-level tools can help by automating many of the design tasks.