A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE
- Resource Type
- Conference
- Authors
- Francese, Pier Andrea; Cevrero, Alessandro; Ozkaya, Ilter; Brandli, Matthias; Menolfi, Christian; Morf, Thomas; Kossel, Marcel; Kull, Lukas; Luu, Danny; Toifl, Thomas
- Source
- 2018 IEEE Symposium on VLSI Circuits VLSI Circuits, 2018 IEEE Symposium on. :267-268 Jun, 2018
- Subject
- Components, Circuits, Devices and Systems
Decision feedback equalizers
Clocks
Receivers
Energy efficiency
Very large scale integration
Insertion loss
Timing
- Language
A decision feedback equalization (DFE) technique suitable for high data-rate I/O link receivers is presented. The technique leverages quarter-rate data slicing to implement a fully speculative 3-tap DFE and uses clock forwarding to reach a speed of 50Gb/s. It corresponds to 20ps timing closure of the most critical path, which is the feedback of the first DFE tap. The RX data-path is implemented in 14nm FinFET CMOS SOI technology. At 0.9V supply the energy-efficiency is 1.6pJ/b when PRBS15 data transmitted at 50Gb/s across a channel with 32.5dB insertion loss are recovered with >30% horizontal margin (BER