Contriving of a novel BIST (built in self-test) digital combinational lock
- Resource Type
- Conference
- Authors
- Sengar, Jitendra Singh; Ghosh, Sudipta; Shekhar, S. Raj; Verma, Praveen; Sharma, Rajat
- Source
- 2013 Fourth International Conference on Computing, Communications and Networking Technologies (ICCCNT) Computing, Communications and Networking Technologies (ICCCNT),2013 Fourth International Conference on. :1-5 Jul, 2013
- Subject
- Communication, Networking and Broadcast Technologies
Computing and Processing
Signal Processing and Analysis
Built-in self-test
Registers
Security
Generators
Random sequences
Automata
Hardware design languages
Digital Combinational Lock
Finite State Machine
BIST
Security system
Verilog HDL
Random Sequence Generator
- Language
This paper presents the design of digital combinational lock by using Finite State Machine. The digital combinational lock presented in this paper is equipped with advanced features wherein the user can set the combination of his or her choice “n” number of times. The inclusion of built in self testing (BIST) capabilities in the present system helps user to determine the lock condition. The source code of the digital combinational lock has been written in Verilog HDL and the designing has been done in Xilinx ISE.