Multi-level p+ tri-gate SONOS NAND string arrays
- Resource Type
- Conference
- Authors
- Friederich, C.; Specht, M.; Lutz, T.; Hofmann, F.; Dreeskornfeld, L.; Weber, W.; Kretz, J.; Melde, T.; Rosner, W.; Landgraf, E.; Hartwich, J.; Stadele, M.; Risch, L.; Richter, D.
- Source
- 2006 International Electron Devices Meeting Electron Devices Meeting, 2006. IEDM '06. International. :1-4 Dec, 2006
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
SONOS devices
Threshold voltage
FinFETs
Nonvolatile memory
Fluctuations
Electron traps
Pulse measurements
Lithography
Dry etching
Resists
- Language
- ISSN
- 0163-1918
2156-017X
Tri-gate silicon-oxide-nitride-oxide-silicon (SONOS) NAND string arrays with p+ gate for multi-level high density data flash applications have been fabricated down to 50 nm gate length for the first time. Thick nitride and top oxide layers have been chosen to achieve large threshold voltage shifts of ΔV th = 6 V at NAND flash compatible times and voltages. In spite of the thick dielectric stack device scalability is not compromised, as shown by simulation for 30 nm gate length. In addition, excellent program inhibit and retention properties as well as tight multi-level threshold voltage distributions have been found.